Welcome to Jurij Silc's Home Page
	Name: Jurij   (pronunciation Yuri) Surname: Silc     (pronunciation Shilz) Address: Computer Systems Department          Jozef Stefan Institute          Jamova 39          1000 Ljubljana, Slovenia
	Phone: +386 61 1773 268     Fax: +386 61 219 385  E-mail: jurij.silc@ijs.si

Biographical Sketch

Born April 8, 1956, Ljubljana, Slovenia 1979 BSc EEng. U Ljubljana, Slovenia 1982 MSc EEng. U Ljubljana, Slovenia 1992 PhD EEng. U Ljubljana, Slovenia 1980-92 Research Assistant, JSI, Ljubljana, Slovenia 1992-95 Postdoctoral Associate, JSI, Ljubljana, Slovenia 1995-   Researcher, JSI, Ljubljana, Slovenia 1986-94 Head of the LCA, JSI, Ljubljana, Slovenia 1994-   Deputy Head of CSD, JSI, Ljubljana, Slovenia

Service to the Profession

Referee, journals:      Informatica      Journal of Computing and Information Technology Referee, conferences:      Information Technology Interfaces 1994      6th Int'l PARLE Conference 1994      The European Design and Test Conference 1995      Parallel Numerics 96 Workshop      5th Euromicro Workshop Parall. Distr. Proc. 1997 Chair, Organizing Committee:      1st Int'l Modula-2 Conference 1989 Member, Programme Committee:      Parallel Numerics 96 Workshop      PPAM'97 Conference      Parallel Numerics 97 Workshop Proceedings Editor:      1st Int'l Modula-2 Conference 1989      Parallel Numerics 96 Workshop

	Areas of Research
	computer architectures multithreaded computing high-level synthesis parallel processing

R&D Projects

1998  1997   1996  1995   1994  1993   1992  1991   1990  1989   1988  1987   1986   MZT

1996-98 Communications and mapping in parallel computers 1995-97 Architectural synthesis of computer systems with testability issues 1994-97 From parallel algorithms analysis to VLSI architecture design for digital signal and image processing 1993-95 Homogeneous parallel computer structures 1993-95 Optimization of computing on processor arrays 1993-95 CEI project: Programming environments, algorithms, applications, compilers and tools for parallel computation 1993 User interface for querying a legal information system 1992 Development of components of control and measurement devices 1991-94 Algorithms for parallel computers and multiprocess systems 1991-93 Small scale hybrid system 1986-92 Computer systems and technologies

Articles in Journals

1998  1997   1996  1995   1994  1993   1992  1991   1990  1989   1988  1987   1986

J.Silc, B.Robic, T.Ungerer: »Asynchrony in parallel computing: From dataflow to multithreading«. Parallel and Distributed Computing Practices, 1(1), 1998. [Abstract] [HTML] [PDF] B.Robic, J.Silc: »Algorithm mapping with parallel simulated annealing«. Computers and Artificial Intelligence, 14(4):339-351, 1995. [Abstract] J.Silc: »Scheduling strategies in high level synthesis«. Informatica, 18(1):71-79, 1994. [Abstract] J.Silc, B.Robic: »Program partitioning for a control/data driven computer«. J. Computing and Information Technology, 1(1):47-55, 1993. [Abstract] J.Silc, B.Robic, J.Buh: »Alpha AXP overview«. Informatica, 17(1):35-40, 1993. [Abstract] B.Robic, P.Kolbezen, J.Silc: »Area optimization of dataflow-graph mappings«. Parallel Computing, 18(3):297-311, 1992. [Abstract] S.Raman, L.M.Patnaik, J.Silc, M.Spegel: »Parallel implementation of VLSI circuit simulation«. Informatica, 15(2):14-22, 1991. [Abstract] J.Silc, B.Robic, L.M.Patnaik. »Performance evaluation of an extended static dataflow architecture«. Computers and Artificial Intelligence, 9(1):43-60, 1990. [Abstract] J.Silc, B.Robic. »Synchronous dataflow-based architecture«. Microprocessing and Microprogramming, 27(1-5):315-322, 1989. [Abstract] L.M.Patnaik, R.Govindarajan, M.Spegel, J.Silc: »A critique on parallel computer architectures«. Informatica, 12(2):47-64, 1988. [Abstract] A.V.S.Sastry, L.M.Patnaik, J.Silc: »Dataflow architectures for logic programming«. Electrotechnical Review, 55(1):9-19, 1988. [Abstract] B.Mihovilovic, P.Kolbezen, J.Silc: »A paradigm of transputer system implementation«. Informatica, 11(4):54-58, 1987. [Abstract] J.Silc, B.Robic: »Data flow based parallel inference machine«. Informatica, 11(4):27-34, 1987. [Abstract] J.Silc, B.Robic: »The review of some data flow computer architectures«. Informatica, 11(1):61-66, 1987. [Abstract] B.Robic, J.Silc: »On choosing a plan for the execution of data flow program graph«. Informatica, 10(3):11-17, 1986. [Abstract]

Conference Papers

1998  1997   1996  1995   1994  1993   1992  1991   1990  1989   1988  1987   1986

J.Silc, B.Robic: »The impact of scheduling and allocation on the performance of massively parallel computers: Experimental results«. Proc. Symposium on Combinatorial Optimization, Brussels, Belgium, Apr. 15-17, 1998, (to appear). U.Kac, G.Papa, F.Novak, J.Silc: »On-line testing of a discrete PID regulator: A case study«. Proc. 23rd Euromicro Conf. New Frontiers of Information Technology Short Contributions, Budapest, Hungary, Sep. 1-4, 1997, pp.- (IEEE Computer Society Press, 1998). B.Robic, J.Silc, R. Trobec: »Reliability and throughput improvements in massively parallel systems«. In E.H.D'Hollander, G.R.Joubert, F.J.Peters, U.Trottenberg (Eds.): Parallel Computing: Fundamentals, Applications and New Directions, Proc. 6th Int'l Conf. Parallel Computing ParCo'97, Bonn, Germany, Sep. 16-19, 1997, pp.-(Elsevier Science, 1998). [Abstract] B.Robic, J.Silc: »Towards better system throughput via static mapping and dynamic allocation«. Proc. 12th Int'l Symp. Computer and Information Sciences, Antalya, Turkey, Oct. 27-29, 1997, pp.454-461. [Abstract] J.Silc, B.Robic: »Processor allocation based on weighted bipartite matching«. Proc. 2nd Int'l Conf. Parallel Processing and Applied Mathematics, Zakopane, Poland, Sep. 2-5, 1997, pp.372-377. [Abstract] B.Robic, J.Silc: »Efficient computation on processor arrays in a multi-user environment«. Proc. 22nd Euromicro Conf. Beyond 2000: Hardware/Software Design Strategies Short Contributions, Prague, Czech Republic, Sep. 2-5, 1996, pp.82-87 (IEEE Computer Society Press, 1997). [Abstract] D.Torkar, J.Silc: »Stereo correspondence through structural description of objects«. Proc. IASTED Int'l Conference Signal and Image Processing and Applications, Annecy, France, Jun. 12-14, 1996, pp.138-141 (Acta Press, 1996). [Abstract] J.Silc,B.Robic: »Dynamic program allocation on the mesh-connected parallel architecture«. In E.H.D'Hollander, G.R.Joubert, F.J.Peters, D.Trystram (Eds.): Parallel Computing: State-of-the-Art and Perspectives, Proc. 5th Int'l Conf. Parallel Computing ParCo'95, Gent, Belgium, Sep. 19-22, 1995, pp.701-704 (Elsevier Science, 1996). J.Silc,B.Robic: »Efficient run-time program allocation on a parallel coprocessor«. In S.Haridi, K.Ali, P.Magnusson (Eds.): EURO-PAR'95 Parallel Processing, Proc. 1st Int'l EURO-PAR Conference, Stockholm, Sweden, Aug. 29-31, 1995, Lecture Notes in Computer Science 966:715-718 (Springer-Verlag, 1995). [Abstract] J.Silc.: »Scheduling and allocation in high-level synthesis«. In A.Bachem, U.Derigs, M.Junger, R.Schrader (Eds.): Operations Research '93, Proc. 18th Symp. Operations Research, Cologne, Germany, Sep. 1-3, 1993, pp.474-477 (Physica-Verlag, 1994). [Abstract] B.Robic, J.Silc: »Fault tolerant mapping onto VLSI/WSI processor arrays«. Proc. 20th Euromicro Conf. System Architecture and Integration, Liverpool, UK, Sep. 5-8, 1994, pp.697-703 (IEEE Computer Society Press, 1994). [Abstract] B.Robic, J.Silc: »Using parallel simulated annealing in the mapping problem«. In C.Halatsis, D.Maritsas, G.Philokyprou, S.Theodoridis (Eds.): PARLE'94 Parallel Architectures and Languages Europe, Proc. 6th Int'l PARLE Conference , Athens, Greece, July 4-8, 1994, Lecture Notes in Computer Science, 817:797-800 (Springer-Verlag, 1994). [Abstract] B.Robic, J.Silc: »Mapping irregular parallel algorithms in VLSI arrays«. Proc. 4th COST #229 WG.1 Workshop on Adaptive Methods and Emergent Techniques for Signal Processing and Communications, Ljubljana, Slovenia, April 1994, pp.169-173 (Slovenian Section IEEE, 1994). [Abstract] B.Robic, J.Silc: »High-performance computing on a honeycomb architecture«. In J.Volkert (Ed.): Parallel Computation, Proc. 2nd Int'l ACPC Conference, Gmunden, Austria, Oct. 4-6, 1993, Lecture Notes in Computer Science, 734:1-13 (Springer-Verlag, 1993). [Abstract] J.Silc, B.Robic: »Program graph partitioning for macro-dataflow«. Proc. ISSM Int'l Workshop on Parallel Computing, Trani, Italy, Sep. 10-13, 1991, pp.198-200 (Acta Press, 1991). [Abstract] B.Robic, P.Kolbezen, J.Silc: »Graph compactor for mapping of algorithms on VLSI processor arrays«. Proc. ISSM Int'l Workshop on Parallel Computing, Trani, Italy, Sep. 10-13, 1991, pp.327-330 (Acta Press, 1991). [Abstract] J.Silc, B.Robic. »MADAME - Macro-dataflow machine«. Proc. Mediterranean Electrotechnical Conf. MELECON'91, Ljubljana, Slovenia, May 22-24, 1991, pp.985-988 (IEEE, 1991). [Abstract] B.Robic, J.Silc, P.Blaznik, P.Kolbezen. »On reducing the dataflow-graph hosting area«. Proc. 5th Annual European Computer Conf. CompEuro 91, Bologna, Italy, May 13-16, 1991, pp.138-142 (IEEE Computer Society Press, 1991). [Abstract] J.Silc, B.Robic. »Efficient dataflow architecture for specialized computations«. Proc. 12th World Congress on Scientific Computation IMACS 88, Paris, France, July 18-22, 1988, pp.4.681-4.684 (IMACS, 1988). [Abstract] B.Robic, J.Silc, P.Kolbezen. »Resource optimization in parallel data driven architecture«. Proc. 5th IASTED Int'l Symp. Applied Informatics, Grindelwald, Switzerland, Feb. 17-19, 1987, pp.86-89 (Acta Press, 1987). [Abstract]

Selected Citations

1998  1997   1996  1995   1994  1993   1992  1991   1990  1989   1988  1987   1986

J.Silc, B.Robic, T.Ungerer: »Asynchrony in parallel computing: From dataflow to multithreading«. Parallel and Distributed Computing Practices, 1(1), 1998.      M. Beck, E. Zehender, T. Ungerer. Architecture-dependent partitioning of dependence graphs. Proc. 6th Euromicro Workshop on Parallel and Distributed Processing, Madrid, Spain, 21-23 January 1998. B.Robic, J.Silc: »Algorithm mapping with parallel simulated annealing«. Computers and Artificial Intelligence, 14(4):339-351, 1995.      B. Robic, B. Vilfan. Improved schemes for mapping arbitrary algorithms onto processor arrays. Parallel Computing 22(5):701-724, 1996. J.Silc: »Scheduling strategies in high level synthesis«. Informatica, 18(1):71-79, 1994.      B. Korousic-Seljak. Task scheduling policies for real-time systems. Microprocessing and Microsystems 18(9):501-511, 1994. B.Robic, J.Silc: »High-performance computing on a honeycomb architecture«. In J.Volkert (Ed.): Parallel Computation, Proc. 2nd Int'l ACPC Conference, Gmunden, Austria, Oct. 4-6, 1993, Lecture Notes in Computer Science, 734:1-13 (Springer-Verlag, 1993).      I. Stojmenovic. Honeycomb networks: Topological properties and communication algorithms. IEEE Trans. Parallel and Distributed Systems 8(10):1036-1042, 1997.      B. Slivnik, R. Trobec. Mapping of Virtual Computer Structure on Mesh-Connected Computers. In E.H.D'Hollander, G.R.Joubert, F.J.Peters, D.Trystram (Eds.), Parallel Computing: State-of-the-Art and Perspectives, Advances in parallel computing, pp.239-245, Elsevier Science Publishers, 1996.      I. Stojmenovic. Honeycomb networks. Lecture Notes in Computer Science, 969:267-1276, 1995. J.Silc, B.Robic: »Program partitioning for a control/data driven computer«. J. Computing and Information Technology, 1(1):47-55, 1993.      B. Benko, M. Ojstersek, V. Zumer. Improvement of duplication scheduling heuristic algorithm with nonstrict triggering of program graph nodes. Proc. 1st Aizu Int'l Symp Parallel Algorithms and Architecture Synthesis pp.227-233, Aizu-Wakamatsu, Fukushima, Japan, 15-17 March 1995, (IEEE Computer Society Press). B.Robic, P.Kolbezen, J.Silc: »Area optimization of dataflow-graph mappings«. Parallel Computing, 18(3):297-311, 1992.      B. Zavidovique, J. Serot, G. Quenot. Massively-parallel data-flow computer dedicated for real-time image-processing. Integrated Computer-Aided Engineering 4(1):9-29, 1997.      R. Trobec, I. Jerebic. Local diagnosis in massively parallel systems. Parallel Computing 23(6):721-731, 1997.      B. Robic, B. Vilfan. Improved schemes for mapping arbitrary algorithms onto processor arrays. Parallel Computing 22(5):701-724, 1996.      J. Serot, G. Quenot, B. Zavidovique. A visual dataflow programming environment for a real time parallel vision machine. Journal of Visual Languages and Computing 6(4):327-347, 1995.      B. Benko, M. Ojstersek, V. Zumer. Improvement of duplication scheduling heuristic algorithm with nonstrict triggering of program graph nodes. Proc. 1st Aizu Int'l Symp Parallel Algorithms and Architecture Synthesis pp.227-233, Aizu-Wakamatsu, Fukushima, Japan, 15-17 March 1995, (IEEE Computer Society Press).      J. Serot, G. Quenot, B. Zavidovique. Functional programming on a data-flow architecture -- applications in real-time image-processing. Machine Vision and Applications 7(1):44-56, 1993.      J. Serot, G. Quenot, B. Zavidovique. A functional data-flow architecture dedicated to real-time image-processing. IFIP Transactions A-23:129-140, 1993. J.Silc, B.Robic, L.M.Patnaik. »Performance evaluation of an extended static dataflow architecture«. Computers and Artificial Intelligence, 9(1):43-60, 1990.      T. Ungerer. Datenflussrechner (dataflow computers). B.G. Teubner-Verlag, Stuttgart 1993. J.Silc, B.Robic. »Synchronous dataflow-based architecture«. Microprocessing and Microprogramming, 27(1-5):315-322, 1989.      T. Ungerer. Datenflussrechner (dataflow computers). B.G. Teubner-Verlag, Stuttgart 1993. J.Silc, B.Robic: »The review of some data flow computer architectures«. Informatica, 11(1):61-66, 1987.      P. Brajak. Performance evaluation and predictions for ISSM based parallel processor architecture. Proc MIPRO '87 pp.5:7-13, May 1987.