B.Robic, P.Kolbezen, J.Silc.
Graph compactor for mapping of algorithms on VLSI processor arrays.
Proc. ISSM Int'l Workshop on Parallel Computing, pp.327-330, Trani, Italy, September 10-13, 1991.

When using hexagonally connected data-driven array as a target computer architecture, and a certain well known algorithm to perform the mapping of program graphs on it, it is known that the results of such mapping generally can be improved. In this paper a software tool is described, named graph compactor, which has been designed to perform area-time optimization of program graph mappings.