R.Trobec, F.Novak, D.S.Prodan.<br>
Design of asynchronous digital multiplex unit - ASIC implementation 
considerations.<br>
<i>Proc. EDAC-ETC-EUROASIC 1994 - User Forum</i>, pp.7-11, Paris, France, 
1994.<p>

The paper describes design phases of an asynchronous digital
multiplex unit initially implemented in EPLD technology. Cost analysis
for the possible transfer into a gate array is presented. Described case
study can serve as an example of the design strategy with intermediate
implementation and performance verification phases. It may also reveal
some specifics of the current electronic product design and manufacturing
in Central and Eastern European electronic market.